1. Field of the Invention
The present invention relates to a capacitor, and more particularly, to a metal-insulator-metal capacitor and method of manufacturing the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for increasing the integration of a metal-insulator-metal capacitor.
2. Discussion of the Related Art
In general, semiconductor circuits are fabricated in and on a semiconductor substrate. Active devices, such as transistors and diodes are formed in the semiconductor substrate. Further, active devices as well as passive devices, such as capacitors and inductors can be formed on the semiconductor substrate. Wiring is also formed on the semiconductor substrate to interconnect to the active and passive devices. The wiring includes wiring lines and vias for interconnection to devices and/or to other wiring lines.
A capacitor includes a first electrode, a second electrode and a dielectric film interposed between the first and second electrodes. Capacitance C of a capacitor is expressed as the following equation (1):C=∈·As/d  (1)In the above equation (1), C denotes capacitance of the capacitor, ∈ denotes dielectric constant of a dielectric material in the capacitor, As denotes surface area in which the first and second electrodes of the capacitor oppose each other, and d denotes thickness of the dielectric film between the first and second electrodes in the capacitor. In accordance with equation (1), the capacitance of a capacitor may be increased by (a) reducing the thickness d of the dielectric film in the capacitor, (b) increasing the surface area As of the capacitor, or (c) using a dielectric material for the dielectric film that has a high dielectric constant ∈.
A conventional capacitor for use in a semiconductor circuit includes a first polysilicon plate, a second polysilicon plate and a dielectric film interposed therebetween. Because the plates of the capacitor are polysilicon, the dielectric film must have a sufficient thickness to prevent shorting between the two plates caused by any malformations of the polysilicon. Such a plate capacitor is a planar or two dimensional type of capacitor. Thus, increasing the surface area As of a conventional planar type capacitor increases the amount of surface area used the semiconductor substrate, which degrades integration. To increase surface area As without decreasing integration, a three dimensional (3D) capacitor is used instead of the planar type capacitor. To reduce the thickness d, metal electrodes with less probability of having malformations are used instead of polysilicon. Capacitors with metal electrodes are otherwise known as metal-insulator-metal (MIM) capacitors.
Conventionally, interconnection between a device and a wiring line or between two wiring lines is done by a plug structure, such as a tungsten plug. Such structures require at least two entirely separate processing procedures including one for forming the plug followed by another one for forming the wiring line. A single processing procedure known as a dual damascene process is used to form both a wiring line and a via from the wiring line to a device or to another wiring line at the same time.
A dual damascene process forms a dielectric layer with a contact hole for a via in a bottom portion of the dielectric layer and a trench in an upper portion of the dielectric layer. Then, a conductive material is provided in the trench and the contact hole to form the wiring line and the via. The via acts like a plug structure in the conventional interconnection structure. Further, the via is integrally connected to the wiring line in the trench because the via is filled with a conductive material while the trench is filled with the same conductive material during the same process step in which the conductive material is deposited. Thus, the dual damascene process eliminates the need to form a plug structure in a separate process from the process of forming the wiring line.
There are two basic ways of initiating a dual damascene process. One way is the trench-first dual damascene in which the trench is first formed in the dielectric layer and then the contact hole for the via is formed. Another way is the hole-first dual damascene, which forms a hole through the dielectric layer and forms the trench in the dielectric layer across the hole such that there is a contact hole in the dielectric layer at the bottom of the trench.
Typically, the processing procedures for forming capacitors are separate from dual damascene process for forming wiring lines with vias. Thus, the formation of capacitors and wiring on a semiconductor substrate is a start, stop, re-start, and stop process in the sense that a wiring forming process is started and stopped so a capacitor forming process can start, and then the capacitor forming process is stopped so that the wiring forming process can restart. The prior art also has other problems that will be explained in reference to prior art shown in FIGS. 7 to 9.
FIG. 7 is a cross-sectional view of an MIM capacitor disclosed in U.S. patent application no. 2006/0009065. A lower electrode 131 of the capacitor is a barrier metal, such as Ta, TaN, Ti and TiN. Barrier metals have a high resistivity. Thus, such a capacitor disclosed in U.S. patent application no. 2006/0009065 can not be used in a high frequency device. Further, the protruding portions 122 of the lower electrode of the capacitor in U.S. patent application no. 2006/0009065 has a height that is not higher than the via portion of the wiring 117.
FIG. 8 is a cross-sectional view of an MIM capacitor disclosed in U.S. Pat. No. 6,620,701. As shown in FIG. 8, a first electrode 18 is formed within a trench of dielectric 14. Then, portions of the dielectric 14 between nodes of the first electrode 18 are dry etched. The first electrode 18 may be damaged by the dry etch. A dielectric film 26 is disposed on the first electrode 18. Conductive lines of a second electrode are provided between the nodes of the first electrode 18 and then an upper electrode of the second electrode is provided on the conductive lines. Then, chemical-mechanical polish (CMP) is performed to planarize the upper surface of the upper electrode of the second electrode. When the CMP of upper electrode is performed, the dielectric film between the first and second electrodes may be revealed by a dishing problem of the CMP.
FIG. 9 is a cross-sectional view of an MIM capacitor disclosed in U.S. Pat. No. 6,638,830. Nodes 28 of a first electrode of the capacitor are in the trench-level of a dielectric layer 18, as shown in FIG. 9. When dry etch is performed prior to forming the second electrodes, the nodes 28 may be damaged. CMP by-products may electrically connect the first and second electrodes of the capacitor together.
FIG. 10 is a cross-sectional view of an MIM capacitor disclosed in U.S. Pat. No. 6,559,004. Nodes 27 of a first electrode of the capacitor are in the via-level 28 of the dielectric layer 22. When CMP of upper electrode is performed, dielectric film 23 may be revealed by the CMP dishing problem.
As can be seen from the above discussion, there is a need for combining a process for forming a capacitor together with a dual damascene process for forming wiring lines and vias. Further, there is a need for a low resistivity metal electrode capacitor, which is compatible with the dual damascene process. Furthermore, there is a need for a high capacity capacitor with high integration.